In many modern applications, FPGA circuit developers design only a portion of an entire FPGA design. For example, one FPGA circuit developer can design a processor core, another FPGA developer can design a memory block, another can design a memory controller, and still others can design other portions of the FPGA design. The various circuit developers may work for a single entity as part of different teams or for different entities (e.g., for different circuit developers in different business enterprises). Because of, for example, the difficulty and expense of designing and verifying a circuit design, and the commerciability of the design, a designing entity may desire to keep the circuit design a secret, or at least desire not to disclose, or limit the disclosure of, the circuit design to other parties such as other developers, users, designers, or customers. A semiconductor intellectual property core, or simply “IP core” or “IP block,” can refer to a unit of logic, a cell, a chip layout, or otherwise to a circuit design to be used in conjunction with other circuits as part of a larger FPGA circuit design. The IP block is the design of, and typically intellectual property of, a particular circuit developer. The IP developer (or “designer”) may sell or license use of the IP block to another developer or user that then implements the IP block into that user's own larger design, which may itself be a part of a larger design.
Although IP blocks can be sent to other parties, such as a user of an FPGA, as a netlist, IP blocks are typically sent at the register-transfer-level (RTL) level, such as in the form of a synthesizable hardware description language (HDL)-implemented design. Because the design is delivered in an HDL form, the user can modify the design at the functional level. However, as described above, because a developer may wish to keep the design secret (e.g., as a trade secret), because of the time and expense involved with verification, or for other reasons, a developer may not want the user to be able to have such access to the functional description of the circuit design. For example, because a circuit developer may not offer a warranty or support for the IP block if the design is modified, the circuit developer may desire to prevent an FPGA user from having access to the functional description of the circuit design. Providing the circuit design to the user as a software netlist can provide better protection against reverse engineering than providing the design in an HDL form, but reverse engineering can still be accomplished. The IP developer may also simply desire to ensure that the end user or customer receives the benefit of the verified implementation for the developer's own goodwill. Additionally, some IP developers are required to have their IP blocks independently verified by a third party (e.g., TÜV Rheinland headquarted in Cologne, Germany) to ensure a product integrating the design will meet functional safety requirements (e.g. the IEC61508 specification). This can be a significantly costly procedure. As such, an IP developer may seek to prevent a second IP user from modifying the IP block so that verification of compliance with functional safety requirements isn't required twice. Additionally, an IP developer may seek to ensure that a verified IP block design is provided to an IP user as it was verified. If the IP developer were to provide an RTL implementation or a netlist implementation of the IP block to the IP user, the IP user's CAD tool might not output the same programming bits for the IP block as the developer intended. Since such methods of transmitting a design do not guarantee that no changes were made to the IP block, the IP user might be required to, or desire to, re-qualify and verify the design.